The breakdown voltage of HV devices on SOI is limited by the device layer thickness and the buried insulator layer thickness. For example, the drain-substrate voltage of LDMOS transistor in “off” state partly drops on the buried insulator layer and partly on the depleted device layer. The handle layer carries no voltage drop, as it does not meet the conditions for deep depletion formation. Increased breakdown voltage may be achieved by either a thicker device layer (making room for larger depletion region), or a much thinner device layer (increasing the critical electric field, Ec, as result of shortened ionization integrating path). The creation of a device layer thicker than a few micrometers, e.g., by epi-Si growth, raises the cost of that layer and complicates considerably the process of trench isolation. In contrast, a device layer thinner than approximately 0.5 μm brings about higher Ec; however it rules out the integration of the HV device in a full BCD platform, thus limiting its applicability. Making a thicker buried insulator layer in order to raise BV is limited by process complexity, cost, and worse heat dissipation capability.
Yamaguci et al. (U.S. Pat. No. 5,874,768) insert electric-field alleviating layer of low (intrinsic) concentration or amorphous silicon in bottom portion of the top silicon layer. This creates a PIN diode (body→new layer→drain) that can carry high voltage. Moreover, the intrinsic concentration of the electric-field alleviating layer allows using same layer in both PLDMOS and NLDMOS. This layer allows negative high voltage at source of NLDMOS and vice versa for PLDMOS. The authors achieved a BV of approximately 125V with layer concentration of 1×1014 cm−3 and top silicon layer of thickness 10 μm and buried oxide layer 0.5 μm thick, which is not believed to be optimal.
The thermal conductivity of SiO2, commonly used as the insulating layer in SOI, is about 1/100 that of Si. Thus a HV device surrounded by insulating layers (lateral buried layer and vertical trenches) is susceptible to buildup of heat and resultant temperature rise. For example, elevated temperature of LDMOS in conduction (“on” state) brings about reduced saturation current due to degraded mobility of carriers. In extreme cases temperature rise may cause thermal destruction. Yamaguchi et al. (U.S. Pat. No. 5,777,365) facilitate heat dissipation by thinning the buried oxide in regions that do not carry high voltage drop, e.g. under body region of an LDMOS. Yamaguchi also considers removing the buried oxide in such low voltage regions, and creating junction isolation instead of dielectric isolation, exclusively for the sake of improved heat dissipation.
Another challenge in processing of a device on SOI is the removal of undesired impurities—usually metal atoms such as copper, nickel, iron, etc.—from device active regions. Such impurities may introduce generation-recombination centers in the energy band gap and affect device performance, depending on their location. These impurities can also degrade gate oxide integrity, increase junction leakage, reduce life-times, etc. Undesired impurity levels in the device layer can be decreased by providing alternative sites (“getters”) away from the device active region. These sites are energetically preferable, and may trap impurities that diffuse, e.g. under thermal drive. Getters have to be stable over the entire process, in order to ensure that gettered metal impurities stay remote from active regions. In SOI wafers the buried insulator layer constitutes a diffusion barrier to impurities such as iron; hence effective gettering is required in the device layer.
Hong et al. (U.S. Pat. No. 5,753,560) provide a method for lateral gettering in SOI wafers, to be performed prior to the formation of the gate dielectric layer. With their process, ion implantation amorphizes dedicated regions in the device layer, and subsequent annealing causes recrystallization, leaving defects that form getters. While this method may work well for small devices, where getters can reside close enough to the gate region, it may be less effective for HV devices that usually occupy large areas. A similar gettering technique employs POCl diffusion in SOI HV platform. It consumes large areas due to Phosphorus diffusion, increases the number of process steps and fabrication costs. It is not effective enough, due to the large distance between gettering site and active device location.
Formation of an electrical contact to the handle layer of an SOI wafer is yet another challenge. Grounded backside is a must in HV SOI ICs in order to prevent electric field buildup due to capacitive charge from isolated devices switching. It has proven crucial for proper functionality of, e.g., HV LDMOS in off-state, non-volatile memory cells, etc. Conventionally, creating a handle contact requires a costly process of etching through the top silicon layer (few um thick) and the buried insulating layer. Gogoi (U.S. Pat. No. 7,122,395) makes an electrical contact to the handle layer for MEMS devices on SOI, while keeping the surface planar, by creating an opening through the device layer and into the SiO2 sacrificial layer, followed by epitaxy that covers the opening and forms a planer surface.
What is needed is a low-cost and reliable SOI HV device that exhibits enhanced (higher) breakdown voltage (BV) than that of comparably sized conventionally-fabricated HV devices. What is also needed is a reliable method for producing such SOI HV devices that can be incorporated with minimal changes into an existing SOI fabrication flow.